The present invention relates to a data processing apparatus and method for performing a shift function on a binary number.
There are many processing operations within a data processing system where it is necessary to perform a shift function on a binary number. For example, it may be desired to shift the binary number in order to shift out a number of leading zeros in the binary number such that, following the performance of the shift function, the resultant binary number has a logic one value in the most significant bit position. One particular situation where such a shift function may be used is during the normalisation of a floating point number. As will be understood, a floating point number is usually expressed by a sign bit, an exponent value and a fraction value. For a normal floating point number, the significand is given by 1.F (F representing the fractional part (the above-mentioned “fraction value”) of the floating point number), and accordingly for normal floating point numbers the most significant bit of the significand is already a logic one value, and accordingly this significand is normalised. However, if the floating point number is in a subnormal range (as indicated by the exponent having a predetermined value), then the significand of the floating point number is 0.F, and accordingly the most significant bit of the significand is 0. Prior to performing operations using such a subnormal floating point number, it is often the case that the floating point number will be normalised by performing a left shift operation on the significand in order to remove all of the leading 0 values, and by then adjusting the exponent value accordingly.
In order to be able to perform a shift function on a binary number, it is necessary to determine the number of leading 0 values in the input binary number, in order to determine the amount of left shift required in order to remove those leading 0 values. There are a number of count-leading zero (CLZ) circuits available which count the number of 0s in a binary number that precede the highest order 1 in that number, and then generate a leading zero count (LZC) indicative of the number of leading 0s.
However, the shift function cannot be performed until the leading zero count is available to identify the amount of shifting required, and this can introduce some significant performance constraints in some situations.
The paper “A Novel Design of a Two Operand Normalisation Circuit” by Antelo et al, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6, Number 1, March 1998, pages 173-176, describes a technique for incorporating the shifting functionality into a counting leading zero operation. However, whilst such an approach can improve the speed of the shift operation, there are various situations where such an approach is impractical. For example, there are many situations where the leading zero count is also required quickly due to it being needed for other purposes, other than for performing the shift function. For example, in the earlier discussed example of floating point numbers, the leading zero count is also required as soon as possible so that the exponent logic can adjust the exponent of the floating point number based on the shift being performed in respect of the significand. The above approach does not produce the leading zero count as quickly as would be desired in such situations.
Accordingly, it would be desirable to provide an improved technique for performing a shift function on a binary number, whilst also improving the speed of generating a count value indicative of a number of contiguous bit positions in the binary number having a predetermined bit value, for example the number of leading 0 bit values in the binary number.